In order to realize high performance in a silicon semiconductor device, it is necessary to make a device minute and multilayer in structure. However, it has become more difficult to improve reliability in metal wiring, as the device has become smaller. In order to improve reliability in metal wiring, it is particularly necessary to make an extremely large recessed volume of metal small enough in the case of forming a metallic plug that is used for improving reliability at an end connection portion for connecting wires of an upper layer and of a lower layer. Recently, a polishing technique has been introduced into a silicon semiconductor process as a means for reducing a recessed volume.
An example of a conventional method for forming a metallic plug using the polishing technology is explained referring to FIGS. 8A-8D as follows. First, an aluminum alloy film is formed on an interlayer dielectric 1, which insulates an upper wire and a lower wire, by a sputter deposition method or the like. After forming a predetermined resist pattern on the aluminum alloy film by a photolithographic process, the extra aluminum alloy film is eliminated by dry etching and the resist is then also eliminated, thus obtaining a conductive layer 3 as shown in FIG. 8A. In this case, an example of metal wiring using an aluminum alloy film as the conductive layer 3 is explained, but the conductive layer 3 may be a conductive layer or diffusion layer such as a polycrystalline silicon or the like.
Next, a dielectric that is a silicone oxide film is formed by a CVD method and the dielectric is planarized through a planarization process, thus forming an interlayer dielectric 2. After forming a predetermined resist pattern on the interlayer dielectric 2 by a photolithographic process, an extra dielectric is eliminated by dry etching and the resist is then also eliminated, thus obtaining an end connection 4. The end connection 4 is used for connecting the conductive layer 3 and another conductive layer formed thereon, and is open so that the surface of the conductive layer 3 is exposed.
As a next step, an adhesive layer 5 having a layered structure of a titanium nitride film and a titanium film is formed by a sputter deposition method or the like as shown in FIG. 8B. A tungsten film 6 as a filling film is then formed using a CVD method so as to fill in the end connection 4 completely as shown in FIG. 8C. The film thickness of the tungsten film 6 is about 0.3 .mu.m-1.0 .mu.m except for the end connection 4 portions.
Finally, a metallic plug 7 is obtained by polishing the tungsten film 6 and the adhesive layer 5 using a polishing device until a part of the interlayer dielectric 2 where the end connection 4 is not formed is completely exposed as shown in FIG. 8D. In a slurry used in the polish, alumina is used as an abrasive grain, and iron nitrate, a hydrogen peroxide solution, potassium iodate or the like is used for adjusting pH.
There is no big difference of elevation between the surface of the interlayer dielectric 2 exposed and that of the metallic plug 7, since tungsten is eliminated by polishing. As a result, the recessed volume at the end connection 4 portions after eliminating the tungsten film 6 can be 0.1 .mu.m or less, thus obtaining a highly reliable conductive layer.
However, in the conventional method mentioned above for forming a metallic plug, when the variation in a polishing rate within a substrate in the case of polishing the tungsten film 6 is not small enough with respect to the variation within a substrate in the case of forming a tungsten film, the polishing time until the interlayer dielectric 2 is exposed is different at different places within the substrate. When the polishing time is different, a portion 8 of the adhesive layer 5 that can not be eliminated is created within the substrate as shown in FIG. 8D. As mentioned above, in the case where the adhesive layer can not be eliminated, reliability in a semiconductor device decreases, since a short occurs between conductive layers in the same layer.
Furthermore, even in the case where polishing is conducted only for eliminating the whole tungsten film 6 and adhesive layer 5 within the substrate, a difference of elevation (erosion) 9 depending on a pattern density of the end connection 4 occurs on the surface of the interlayer dielectric 2, since an area having a rapid polishing rate is overpolished. As mentioned above, pattern formation in a photolithography process becomes difficult, when difference of elevation occurs on an interlayer dielectric. Moreover, height of a metallic plug is different according to the difference of elevation of an interlayer dielectric, which causes great variations in resistance at an end connection. As a result, reliability decreases.